hands-on fpga project design from scratch using verilog

Learn FPGA Design with SystemVerilog! This course provides a comprehensive, hands-on approach to creating a real-world FPGA project. You'll gain practical skills in RTL design, synthesis, and verification, all using free software.

We'll start by mastering the process of translating design specifications into functional input/output ports. Then, you'll learn how to effectively decompose complex designs into manageable modules and further refine them into sub-modules.

I'll guide you through the physical aspects of your design using Logism, a powerful free FPGA analysis tool, while leveraging Quartus for the actual FPGA design and implementation. Both Logism and Quartus are readily available for free download, making this a cost-effective learning experience.

This course culminates in a hands-on assignment where you'll apply your knowledge to build a fully functional 5-hand poker player chip. We'll delve into the game design and model, exploring all the necessary steps and stages before solidifying the design specifications.

From the ground up, we'll work together to create a working FPGA design. Throughout the process, we'll utilize simulation in both Logism and Quartus to ensure functionality. Finally, we'll test the final design and analyze its real-world operation.

Key Skills You'll Acquire:

• FPGA Design Fundamentals
• SystemVerilog RTL Design
• FPGA Synthesis
• RTL Simulation & Verification
• Logism for Physical Analysis
• Quartus Prime for FPGA Implementation
• Module Decomposition & Design
• Hands-on Project Development