FPGA Design with VIVADO HLS -High Level Synthesis

Unlock the power of High-Level Synthesis (HLS) for accelerated FPGA design! This course guides you through a modern approach to FPGA development using C/C++, bypassing the complexities of traditional HDL/RTL coding.

What you'll learn:

• HLS Fundamentals: Master the basics of HLS design and C-simulation.
• Computer Vision Application Development: Learn to design real-time computer vision applications, including Sobel Edge Detection.
• Project Lifecycle: Cover the entire HLS project lifecycle:
  • Creating new HLS projects.
  • Running C simulation for verification.
  • Synthesizing HLS projects to Verilog/VHDL and System C.
  • Performing C/RTL co-simulation for seamless integration.
  • Exporting HLS designs as IP cores for use with VIVADO IP Integrator.
• Hands-on Lab Experience: Gain practical skills through labs focusing on:
  • Designing and implementing a Counter in C++.
  • Creating a Matrix Multiplier for high-performance computations.
  • Developing a Frequency Modulator for signal processing.
  • Designing a Numerically Controlled Oscillator (NCO).
• Computer Vision Libraries: Explore the extensive library of C/C++ libraries available for HLS, including OpenCV for advanced image and video processing. HLS simplifies complex tasks like video/image processing and mathematical computations.
• Zybo FPGA Implementation: Integrate your exported HLS projects with the Zynq Processing System using VIVADO IP Integrator and implement/test them on a Zybo FPGA.
• Sobel Edge IP Design: Specifically, learn to design a Sobel Edge IP core in HLS, export it to VIVADO, and then implement and test it on a Zybo FPGA.

By the end of this course, you will be able to:

• Design HLS projects from scratch.
• Simulate and verify your designs effectively.
• Synthesize C/C++ code into hardware.
• Implement and export HLS designs as IP cores for FPGA integration.

This course is ideal for engineers looking to accelerate FPGA development and leverage the power of C/C++ for hardware design.