ASIC Verification using System Verilog (SV) + Project Demo

System Verilog Course: Master Digital Design & Verification

This comprehensive System Verilog course is designed for learners of all levels, from beginners to experienced engineers. You'll be able to grasp core concepts and practical applications within a few weeks of focused study. The course is structured into two parts, with hands-on labs to reinforce learning.

Course Syllabus:

Section I: Fundamentals of System Verilog

• Session 01: ASIC Flow & Verilog Refresh
  • Understanding the ASIC design flow and its importance in digital hardware development.
  • Verilog Refresh: A quick review of essential Verilog concepts.
  • Lab 1: Verilog Testbench Development: Learn to create effective testbenches for verifying your designs.
• Session 02: System Verilog Introduction & Data Types
  • System Verilog Introduction: Explore the key features and benefits of System Verilog.
  • Data Types: Master various data types in System Verilog for efficient design.
  • Lab 2: Programs with Various Data Types: Practical exercises using different data types.
• Session 03: Operators, Control Statements & Loops
  • Operators: Learn and apply different operators in System Verilog.
  • Control Statements: Understand and utilize if, else, case statements.
  • Loops: Master for, while, and repeat loops for efficient code.
  • Lab 3: SV Constructs Practice: Hands-on practice with System Verilog constructs.
• Session 04: Arrays & Queues
  • Arrays: Work with different types of arrays in System Verilog.
  • Queues: Utilize queues for data communication and synchronization.
  • Lab 4: Arrays & Queues Constructs Practice: Practical exercises focusing on array and queue usage.
• Session 05: OOPs - Classes & Objects
  • OOPs (Object-Oriented Programming): Learn the principles of OOP in System Verilog.
  • Classes & Objects: Define and use classes and objects for modular design.

Section II: Advanced System Verilog Techniques

• Session 06: Randomization & Constraints
  • Randomization: Generate random test data for comprehensive verification.
  • Constraints: Apply constraints to control the behavior of your designs.
  • Lab 6: Randomization: Practical application of randomization techniques.
• Session 07: Inter-Process Communication
  • Inter-Process Communication: Understand how different processes communicate with each other.
  • Mailbox, Semaphores & Queues: Utilize these mechanisms for synchronization and data exchange.
  • Lab 7: Use of Mailbox, Semaphores and Queues: Hands-on exercises with communication primitives.
• Session 08: Interfaces
  • Interfaces: Define interfaces for modular and reusable design.
  • Mod Ports & Clocking Blocks: Understand the role of mod ports and clocking blocks in interfaces.
  • Lab 8: Use of Interfaces, Mod Port, Clocking Block: Practical implementation of interfaces.
• Session 09: Testbench Development
  • Testbench Development: Create robust testbenches for verifying System Verilog designs.
  • SV Constructs for Driver/BFMS: Utilize System Verilog constructs for creating drivers and BFMS (Basic Functional Model Simulator) testbenches.
  • Lab 9: Use of SV constructs for driver/BFMS: Practical testbench development exercises.
• Session 10: Code & Functional Coverage
  • Code Coverage: Measure the extent to which your code is exercised.
  • Functional Coverage: Verify that your design meets its functional requirements.
  • Lab 10: Simulate an example for coverage: Simulate examples and analyze code/functional coverage.

Course Highlights:

• Practical Examples: The course includes numerous example codes to illustrate key concepts.
• Industry-Standard Simulators: Some programs are simulated using industry-standard simulators.
• Protocol Example: A complete protocol example is developed with a testbench and test cases.
• Assignment-Based Learning: Assignments provide valuable practice in code writing, testbench development, and test case creation.

This System Verilog training will equip you with