Arm Barriers 101: Part #2: How barriers work in hardware

Dive deeper into the Arm® Architecture with Part 2 of our Barriers 101 training course. This comprehensive program provides a thorough understanding of barriers within Arm-based systems, targeting software engineers developing system-level software for Arm platforms. We cover everything from the firmware layer to the kernel, hypervisor, and device drivers.

In this course, you will master:

• Arm AMBA®-based cache coherent interconnects: Understand the inner workings of these critical components.
• Shareability domains: Learn how they are defined in hardware for optimized performance.
• Barrier broadcasting: Explore how barriers function when broadcast across the interconnect.
• Internal CPU barrier handling: Discover how barriers are managed within the CPU itself.

Whether you're a beginner just starting with Arm Barriers or a seasoned expert in the Arm Architecture, this course is designed for you. We offer a unique, in-depth perspective, explaining how things work and, crucially, why.

Learning is reinforced with practical application: Test your knowledge with 30 multiple-choice quiz questions, each accompanied by a detailed video walkthrough of the question and answer.

Expert-led instruction: This course is written and produced by Ash Wilding, a recognized trainer and former lead technical trainer at Arm, with experience as a kernel engineer at both Amazon AWS and Apple. Gain invaluable insights from a seasoned professional.