Aprende Open-Source: Uso de Openlane para el flujo RTL2GDS

Discover the fascinating world of chip design! This course delves into the intricate process of creating the integrated circuits that power our modern lives – from smartphones and smartwatches to powerful processors, GPUs, TVs, and radios. You'll gain a comprehensive understanding of how these essential components are brought to life.

The journey begins with defining specifications, followed by RTL design using Verilog, incorporating rigorous verification steps. Next, you'll explore logic synthesis and physical synthesis using Openlane, an open-source platform. This leads to the generation of the crucial GDS file, which contains the transistor-level information needed for chip fabrication.

Before sending the GDS to a foundry (chip manufacturer), thorough front-end and back-end verification are essential to ensure functionality. Understanding these stages is key to grasping the complexity of the entire process.

The chip manufacturing process itself takes place in highly controlled cleanrooms to prevent microscopic particles from causing defects.

For practical demonstration, we utilize WSL (Windows Subsystem for Linux) with Openlane, leveraging a suite of open-source tools including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, and KLayout. We'll also explore scripts designed to optimize each stage of the design flow. This course provides a deep dive into the tools and techniques used in modern integrated circuit design.